Current steering DACs are widely used in applications requiring both high speed and high linearity. FIG. 1A schematically illustrates a conventional digital-to-analog interface including a digital signal source 10, an encoder 12, and a current steering DAC 14 which includes a driver circuit (switch driver array) 16 and a DAC switch array (core DAC) 18. A digital signal (code) from the digital signal source 10 is supplied to the driver circuit 16 through the encoder 12, and converted into an analog signal by the DAC switch array 18.
FIG. 1B schematically illustrates an example of the switch array 18 of a segmented current steering DAC having thermometer-coded upper seven bits (MSB) and binary coded lower 5 bits (LSB). As shown in FIG. 1B, a typical current steering DAC includes current elements (current sources) 20 which are switched by switches (SW) 22 to a load (resistance) 24 according to the input digital data. In this example, the switch array 18 includes 132 switches 22. The first five switches (LSB: 1 to 5) are for the binary code and thus are coupled to the binary-weighted current sources 20 (I to 16I). The remaining 127 switches 22 are for the thermometer code (MSB: 7 to 132) and thus coupled to the identical current sources 20 (32I). The corresponding output of the switch driver 16 drives each switch 22 so as to steer the corresponding current source output to one DAC output (VoutP) or its complementary (VoutM).
In most high-speed applications, a fully differential implementation is employed and the load consists of a pair of identical resistors. Furthermore, a fully segmented architecture or one which is heavily segmented is typically used to enhance the dynamic behavior. FIGS. 2A and 2B schematically illustrate a typical DAC 30 and a corresponding bias generator 40. The DAC 30 includes N identical unit currents sources 32 (32-1, 32-2, . . . , 32-N) which are steered to either one of the DAC output 36a (OUTP) or output 36b (OUTM) based on the input digital code. As shown in FIG. 2B, the bias generator 40 creates constant bias voltages VON (a lower voltage in this example) and VOFF (a high voltage in this example) that are applied in a complementary fashion to each of the switch transistors 34 (34-1a, 34-1b, . . . 34-Na, 34-Nb) through driver circuit switches 39. It is assumed that the switch transistors 34 are operated in saturation region to achieve best dynamic performance. For example, the ON bias voltage VON is applied to the transistor 34a while the OFF voltage VOFF is applied to the transistor 34b such that only the transistor 34a conducts and the current I is driven through the output node 36a (OUTP).
Typically, the current sources 32 are realized using transistors as shown in FIG. 3A. In this widely used circuit topology, one of the major limitations of the dynamic performance of the DAC (e.g., spurious free dynamic range (SFDR)) is the finite impedance of the current sources 32 at the operating frequency. Since the total impedance Z seen at the tail node 38 is not infinite, the output signal OUTP or OUTM appears at the tail node 38, depending on whether the switch 34-a or 34-b conducts. Hence, a partially rectified and attenuated version of the output waveform (a signal swing) shows up at each tail node 38. FIG. 3B schematically illustrates an equivalent circuit when one of the switches is conducting. The current I is not constant as it should be, but varies as a function of a voltage (Vtail) at the tail node 38 in a signal-dependent manner.
FIG. 4A schematically illustrates several non-linear capacitances connected to nodes in the conventional DAC 30, which are inherently formed because of the semiconductor process structure of the transistors in the circuit. FIG. 4B schematically illustrates the corresponding bias generator 40 for the DAC 30. These capacitances are due to the reverse biased junction diodes 42, 44a and 44b that exist at the source and drain junctions of CMOS transistors. A non-linear, signal-dependent current flows through these diodes 42, 44a and 44b, which is essentially subtracted or added to the current (IDC1, . . . , IDCN) which would nominally flow into the load (R). Although the differential operation of the DAC switching suppresses the even order harmonics, the rectification process combined with non-linear junction capacitors generates odd order harmonics which cannot be suppressed. This distortion mechanism is the dominant one at mid to high digital-to-analog conversion speeds.
All conventional solutions known to the applicants try to minimize the non-linear current flowing into and out of the tail node 38. One of such conventional solutions is the “brute force” approach, which consists of connecting source-body of the switch transistors. This approach essentially bootstraps the diodes at the source of switch transistors 34a and 34b. However, the drain diode 42 of the current sources IDC continues to conduct non-linear current. Furthermore, a large capacitance due to the N-well where the PMOS switches reside, is added to the tail node 35. N-well is now biased at a lower potential that reduces the reverse bias on it and hence increases both the well and junction capacitances. Particularly, the junction capacitances at the drain of the switches 34 (i.e. those connected to OUTP and OUTM, not shown) will be increased. Although this topology is not as sensitive to these capacitances, a large increase in the capacitances will slow down the rise/fall times (in a non-linear and pattern dependent way) and leads to distortion. In accordance with the applicants' simulation results, the brute force approach led to worse distortion performance.
FIGS. 5A and 5B schematically illustrate an example of another conventional approach to connect the tail node 38 to the bulk 46 of the switch transistors 34a and 34b after a level shift and buffering operations. This will also essentially bootstrap the diodes 44a and 44b associated with the switch transistors 34a and 34b. Since these diodes 44a and 44b will not conduct anymore, a significant portion of the non-linear current can thus be eliminated. By biasing the bulk of the switch transistors close to supply voltage Vcc, as shown in FIG. 6, the junction reverse bias can be increased compared to the above-mentioned solution.
The diodes associated with the switches are bootstrapped, but the N-well 50 now sees all the disturbance at the tail node. The drain-to-N-well junction diodes 52 which form a path between the N-well and the outputs (OUTP, OUTM) carry some of this disturbance back to the output. Furthermore, similar to brute force approach, the N-wells for the switches must all be separated which can lead to significant area penalty. An amplifier/level shifter is needed for each unit current source that can be very power costly for heavily segmented topologies.
Also, this approach still leaves the drain junction diode 42 (see FIG. 5A) associated with the current source 32, unless current source 32 and switch 34 share the same N-well which would lead to even more disturbances. Finally, this approach requires that the switches 34 be put in separate wells. For a PMOS type of switch, a standard CMOS process will handle this requirement but for an NMOS switch, an extra and costly deep N-well option would be necessary. In simulations, this approach did not improve the SFDR at all. Results were similar to the case when no special technique is employed.